Field programmable gate array based digital lock-in amplifier for highest resolution heterodyne interferometer

In this work the electronics for a highest resolution heterodyne interferometer is presented. It comprises an analog front-end, a high speed dual channel analog-to-digital converter and a field programmable gate array for high speed, low latency signal processing. The gate array contains a system on chip (formulated in a hardware description language), consisting of the main processing block (lock-in algorithm) combined with a 32 Bit CPU and additional periphery controllers. Output data is streamed over a high speed serial bus, USB2 or a fiber link. For different uses the firmware and the main processing block may be substituted, while the rest of the system (hardware & software) may remain the same. The underlying electronicplatform and evaluation concept is very versatile and can be used for many different interferometric (homodyne and heterodyne alike) concepts or completely different signal acquisition tasks.